1. Technical Field
The present invention relates generally to image display apparatus and more particularly to an image display apparatus for superimposing a digital image including characters and graphic titles on an image to be displayed according to a composite signal in a standard method under a rule, for instance, in the NTSC method. The present invention further relates to an image display apparatus having a so-called display digital positioning circuit (hereinafter simply called a "digital positioning circuit") containing a digital counter for determining a display position, such as a CRT display apparatus, a liquid crystal display apparatus and a plasma display having matrix pixels.
2. Background Art
FIG. 3 is a block diagram illustrating the configuration and operation of an image display apparatus equipped with a conventional digital positioning circuit, especially depicting its character image signal generating circuit portion.
The character image signal generating circuit 15 is provided with a display data RAM 5 for storing a plurality of character codes to be displayed.
In order to write a character code W supplied from a microcomputer 1 to the display data RAM 5, this circuit is provided with a write address register 2 for holding an address signal A out of control/data signals B from the microcomputer 1, a write data register 3 for holding the character code W, a write synchronizing circuit 4 for generating a write synchronizing signal S according to the control signal therein, and an address selecting circuit 6 for generating an address signal U directed to the display data RAM 5 on receiving the write signal S from the write synchronizing circuit 4.
In order to read a display character code G from the display data RAM 5, the character image signal generating circuit 15 is provided with a vertical address counter 12 for generating a line selecting signal R on receiving a vertical synchronizing signal V and a horizontal synchronizing signal H from a synchronizing signal separating circuit 13 and for applying the line selecting signal R to the address selecting circuit 6; an oscillating circuit 11 for generating a dot clock D on receiving the horizontal synchronizing signal H; and a horizontal address counter 10 for generating a column selecting signal C on receiving the horizontal synchronizing signal H and the dot clock D and for applying the column selecting signal C to the address selecting circuit 6 and the write synchronizing circuit 4.
In order to display a pattern of the character code thus selected, the character image signal generating circuit 15 is further provided with a character generator 7 for generating a character pattern P equivalent to one line out of the pattern equivalent to one character on receiving an address signal L generated in the address selecting circuit 6 and the character code G thus selected, and a serial converter circuit 8 for sequentially outputting a character pattern having a plurality of bits equivalent to one line dot by dot through the dot clock D. The output signal of the serial converter circuit 8 is combined with another image signal E before being applied to CRT 9 on which a superimposed image is displayed.
A description will subsequently be given of the operation of the character image signal generating circuit 15 thus arranged when the character code W supplied from the microcomputer 1 is written to the display data RAM 5.
When the microcomputer 1 supplies a character code to be written to the display data RAM 5 as its data to the write data register 3 according to the control/data signal B, the write data register 3 as a recipient holds the data as the character code W and then supplies the data to the display data RAM 5. When the microcomputer 1 supplies an address of the display data RAM 5 to be written thereto as its data to the address register 2 according to the control/data signal B, the write address register 2 as a recipient holds the address signal A and supplies it to the display data RAM 5. When the microcomputer 1 supplies to the write synchronizing circuit 4 information about the fact that the write address register 2 and the write data register 3 respectively hold the address signal A and the character code W in the form of a control signal according to the control/data signal B, the write synchronizing circuit 4 as a recipient tries to apply a write synchronizing signal S to the display data RAM 5.
At this time, however, the write synchronizing circuit 4 outputs the write synchronizing signal S while avoiding the timing at which the character code G is being read from the display data RAM 5, provided that the display character code G selected by the address signal U generated by the address selecting circuit 6 that has received the line selecting signal R and the column selecting signal C is read in synchronization with the horizontal synchronizing signal H and the vertical synchronizing signal V. The illustration of an input signal directed to the write synchronizing circuit 4 necessary for making the above-noted decision has been omitted in FIG. 3. On receiving the write synchronizing signal S, the address selecting circuit 6 selects the address signal A and supplies this signal to the display data RAM 5 as the address signal U, whereby the character code W is written to the address designated by the address signal U in the display data RAM 5.
A description will subsequently be given of the operation of the circuit at the time the character code G to be displayed is selected and read from the display data RAM 5. On receiving the vertical synchronizing signal V, the vertical address counter 12 initializes its count and on receiving the horizontal synchronizing signal H, it counts up the value and outputs the line selecting signal R for determining the vertical position of a scanning line. On receiving the horizontal synchronizing signal H, the oscillation circuit 11 initializes the oscillation phase, and generates and outputs the dot clock D of a frequency corresponding to the horizontal scanning speed of the scanning line. On receiving the horizontal synchronizing signal H, the horizontal address counter 10 initializes its count and on receiving the dot clock D, it counts up the value and outputs the column selecting signal C for determining the horizontal position of the scanning line. The address selecting circuit 6 receives the line address signal R and the column address signal C thus generated, generates the address signal U intended for the display data RAM 5 and the address signal L intended for the character generator 7 by subjecting these address signals to computation in conformity with the corresponding storage modes, and supplies the results to the display data RAM 5 and the character generator 7, respectively.
On receiving the address signal U, the display data RAM 5 reads the character code G prestored at the address designated thereby and supplies it to the character generator 7. The character generator 7 may be a ROM for storing character patterns, for instance. On receiving the character code G, the character generator 7 selects a pattern (in a matrix configuration) equivalent to one character corresponding to the code and on receiving the address signal L, and outputs the character pattern P equivalent to one line in the pattern equivalent to the one character. The serial converter circuit 8 is mainly formed with a shift register and latches the character pattern P having a plurality of bits and, on receiving the dot clock D, outputs the dots one after another accordingly.
The image signal generated in the character image signal generating circuit 15 and sequentially output therefrom dot by dot is combined with the image signal E separated from a composite image signal F and applied to CRT 9. In this example, the vertical and horizontal coordinate positions of the display picture are determined by the line selecting signal R from the vertical address counter and the column selecting signal C from the horizontal address counter. Further, a dot image to be superimposed on the display image with the coordinates designated out of the coordinate positions determined as noted above is generated from the address selecting circuit 6, the display data RAM 5 and the character generator 7. Therefore, the determination of the display position of the dot image to be superimposed on the display picture is based on the counts given by the vertical address counter 12 and the horizontal address counter 10, the dot clock from the oscillation circuit 11 and the address selecting circuit 6, these constituting a digital positioning circuit.
As a specific example of the image display apparatus having the prior art digital positioning circuit, the character image signal generating circuit has been described. The vertical synchronizing signal V received by the vertical address counter 12 will subsequently be described.
The synchronizing signal separating circuit 13 is supplied with the composite image signal F in the standard method determined under the rule; generates the horizontal synchronizing signal H normally through the steps of extracting the horizontal synchronizing signal H from the composite image signal F by means of a high-pass filter formed with a differentiating circuit, and subjecting the signal thus extracted to wave shaping via an amplifier, a comparator or the like; and generates the vertical synchronizing signal V through the steps of extracting the vertical synchronizing signal V therefrom by means of a low-pass filter formed with an integrating circuit, and subjecting the signal thus extracted to wave shaping via the amplifier, the comparator or the like. The vertical synchronizing signal V thus generated resets the vertical address counter 12 at its trailing edge timing, whereby the vertical position is initialized.
However, the composite image signal F may pick up noise during the radio transmission, and its signal level may fluctuate vertically, which results in a difference of 1/2 H synchronizing timing between odd and even number lines, depending on the display image interlacing, and which also affects the vertical synchronizing signal V separated by the integrating circuit from the composite image signal F. Although the leading edge timing of the vertical synchronizing signal V is relatively stable, its trailing edge timing tends to become unstable (see X, Y of the signal V in the waveform chart of FIG. 2(b)).
On the other hand, the vertical address counter 12 receives the signal V in the waveform chart of FIG. 2(b) and is cleared while the signal remains at an "L" level. Consequently, the count starting timing fluctuates. In other words, the sequential relation between the line selecting signal R output from the vertical address counter 12 and the horizontal synchronizing signal H is unstable when the vertical synchronizing signal V is directly input to the reset input terminal of the vertical address counter 12, and thus the display position of the digital image tends to move up and down by one scanning line.